rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a EVAL-AD974CB one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 evaluation board ad974 4-channel, 16-bit, 200 ksps adc features versatile analog signal conditioning circuitry jumper selectable analog input ranges analog and digital prototyping area flexible power and grounding schemes on-board reference and buffers 16-bit serial and parallel buffered outputs ideal for dsp and data acquisition card interfaces eval-control board compatibility pc software for control and data analysis general description the EVAL-AD974CB is an evaluation board for the ad974 four-channel, 16-bit data-acquisition system. the ad974 is capable of a 200 ksps throughput rate, operates from a single +5 v supply and uses a flexible serial interface. the ad974 evaluation board is designed to demonstrate the adcs performances and to provide an easy to under- stand interface for a variety of system applications. a full description of the ad974 is available in the ad974 data sheet and should be consulted when using this evaluation board. functional block diagram signal conditioning ad845 ref 2.5v ad780 va 1 vb 1 va 4 vb 4 bip ref data dataclk busy r/ c a0 a1 wr2 wr1 sync cs pwrd ext/ int va 2 vb 2 va 3 vb 3 data shift reg b u f f e r s ad974 96-pin connector 6 5v 6 12v v cc selectable supply 40-pin connector 20-pin connector ain1 ain2 ain3 ain4 selectable input range the EVAL-AD974CB is ideal for use as either a stand-alone evaluation board to interface with customer application, or with the eval-control board, also available from analog devices. the design offers the flexibility of applying external control signals and is capable of generating 16-bit conversion results as both serial and parallel buffered outputs. on-board components include an ad780, a +2.5 v ultrahigh precision bandgap reference, an ad845 signal conditioning op amp, and digital buffers. the board interfaces with a 96-pin connector for the eval-control board, a 20-pin idc connector for both externally applied control signals and serial output interfaces, and a 40-pin idc connector for parallel out- put data. smb connectors are provided for the low noise ana- log signal source and bnc connectors are provided for an external data clock and an external read/convert input.
EVAL-AD974CB C2C rev. 0 operating the EVAL-AD974CB the ad974-cb is a four-layer board carefully laid out and tested to demonstrate the specific high accuracy performance of the device. figure 2 shows the schematics of the evaluation board. figure 3 shows the component side silkscreen. the layouts of the board are given in: component layer C figure 4 power layer C figure 5 ground layer C figure 6 circuit side layer C figure 7. the ad974-cb is a flexible design that enables the user to choose among many different board configurations. the avail- able test points are listed in table iv and a description of each selectable jumper is listed in table v. the evaluation board schematic shows the factory installed jumper selections. the ad974 is configured for 10 v input range on each channel, powered through the eval-control board, the ad780 external reference applied to the ref pin and on-board r/ c generation used. the serial interface is con- figured to operate with its internal data clock, dclk. conver- sion data is available at the outputs of two 8-bit shift registers, u4 and u5, for parallel transfer via the 40-pin idc connector, j4, or the 96-pin din connector, p5. additionally, conversion results are available in serial format from the 20-pin connector, p4. the ad974 conversion control inputs, r/ c and cs , are configured to provide continuous conversions with the cs input set low and the r/ c input connected to the output of the counter, u6. power supplies and grounding the ad974-cb power supply connectors and ground planes are configured to provide the multiple power and grounding con- figurations used in most system applications. the evaluation board ground plane is separated into two sec- tions: a plane for the digital interface circuitry and an analog plane for the ad974 and its analog input and external reference circuitry. to attain high resolution performance the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths. the EVAL-AD974CB has three power supply blocks: a single +5 v supply for the ad974 v ana and v dig power pins (p1), a +5 v supply for the digital interface circuitry (p2), and a 12 v supply for the analog signal conditioning circuitry (p3). all supplies are decoupled to ground with 10 m f tantalum and 0.1 m f ce- ramic capacitors. figure 1 shows the recommended power con- nection diagram. analog power supplies digital system power +15v C15v gnd +5v gnd +5v gnd +v cc Cv ee agnd v ana agnd v dig dgnd p4 p3 p1 p2 figure 1. power connection diagram analog input ranges the ad974-cb provides the flexibility of operating the ad974 in each of its specified analog input ranges. through easy to follow jumper selections, the four channels of the ad974 can be operated independently in the bipolar input range 10 v, or in all two unipolar input ranges of 0 v to +4 v, and 0 v to +5 v. table i through table iii list the jumper configurations for each input range. table i. 6 10 v analog input range jumper designation header shunt position jp12, jp27, jp23, jp25 b jp11, jp26, jp22, jp24 b table ii. 0 v to +4 v analog input range jumper designation header shunt position jp12, jp27, jp23, jp25 a jp11, jp26, jp22, jp24 b table iii. 0 v to +5 v analog input range jumper designation header shunt position jp12, jp27, jp23, jp25 a jp11, jp26, jp22, jp24 a table iv. EVAL-AD974CB test points test point available signal tp1 ain1 (buffered) tp2 busy tp3 r/ c tp4 dgnd tp5 vdig tp6 agnd1 tp7 sync tp8 dclk tp9 data tp10 cap tp11 agnd tp12 ain1 (smb) tp13 Cvcc tp14 +vcc tp15 vana tp16 agnd tp17 r/ c (bnc)
C3C rev. 0 EVAL-AD974CB eval-control board interface the EVAL-AD974CB interfaces to the eval-control board through the 96-pin connector. running the EVAL-AD974CB software software description the EVAL-AD974CB comes with software for analyzing the ad974. through the eval-control board one can perform a histogram to determine code transition noise, and fast fourier transforms (ffts) to determine the signal to noise ratio (snr), signal to noise plus distortion (snrd) and total harmonic distortion (thd). the front-end pc software has three screens as shown in figures 8, 9 and 10. figure 8 is the setup screen where channel selection, input voltage range, sample rate, number of samples are selected. figure 9 is the histogram screen, which allows the code distri- bution for dc input and computes the mean and standard de- viation. figure 10 is the fft screen, which performs an fft on the captured data, computes the signal-to-noise ratio (snr), signal to noise plus distortion (snrd) and total harmonic distortion (thd). software installation the ad974-cb software runs under dos 4.0 or higher. it requires a minimum of 386-based machine, with 500 kb of base ram and 500 kb of free hard disk space. it may be necessary to disable some tsrs (network tsrs for example) or load them into high memory, to ensure that adequate base memory is avail- able. operation under windows ? 3.x is not recommended since the windows com interrupt can interfere with communication between the pc and the eval-control board. for pc running under windows 95, it is recommended to shut it down using the option restart with the computer in ms-dos mode. the ad974-cb software installation process is: C create a new directory on the main pc drive and label this ad974. C copy into this directory all files contained in the disk that accompanies the EVAL-AD974CB. C the software can be started by typing ad974. note that the mouse driver on the pc should be enabled before running the software. if this has not been loaded, the program will not run. table v. jumper description jumper designation function jp1 jp1 controls the state of the ad974 power-down pin, pwrd. with jp1 in position b, conversions are inhibited and the ad974 power consumption is significantly reduced. for normal operation of the ad974, jp1 should be in position a. jp2 jp2 selects the ext/ int input to the ad974. set jp2 to position b and the ad974 requires an external data clock to transmit data. position a chooses the internal clock mode. jp3 jp3 allows use of an external dclk. when j2 is in position a, internal clock mode is used and jp3 should be removed . when j2 is in position b, external clock mode is used and the signal ext dclk from bnc connector, j2 is applied to the dclk input of the ad974. jp4 with jp5 set to position a, jp4 selects the signal source for the r/ c input to the ad974. set jp4 to position a to use the on-board 200 khz signal from the 74hc190. select position b to use the external r/ c signal from the bnc connector, j1. jp5 with jp5 in position a, the r/ c input to the ad974 is applied from either the 74hc190 or the external source, j1. with jp5 in position b, the r/ c input is a buffered signal (fl0) from the eval-control board and an input from the 20-pin idc connector. jp6 jp6 selects the wr2 input to the ad974. with shunt header in jp6, the ad974 wr2 input is tied to a logic low. when shunt header in jp6 is removed, the ad974 wr2 input comes from the 20-pin idc connector. jp7 jp7 selects the wr1 input to the ad974. with shunt header in jp7, the ad974 wr1 input is tied to a logic low. when shunt header in jp7 is removed, the ad974 wr1 input comes from the 20-pin idc connector. jp8 jp8 selects the cs input to the ad974. with shunt header in jp8, the ad974 cs input is tied to a logic low. when shunt header in jp8 is removed, the ad974 cs input comes from the 20-pin idc connector. jp9 jp3 allows use of an external read clock, ext rclk. with shunt header in jp9, the ad974 busy signal enables the data reading. when shunt header in jp9 is removed, the signal ext rclk from bnc connector, j5 enables the data reading. jp10 with jp10 set to position a, gain adjustment for the ad974 is possible. position b selects the ad780 for use as an external reference. remove the shunt header of jp10 to use the ad974 internal reference without gain adjustment. jp11, jp12 these two jumpers set the analog input ranges for channel 1 according to table i through table iii. jp13 with jp13 tied to position a, the analog channel 1 input comes from either the analog signal source (ain1) from j3, or the output of the op amp, u3. set to position b, the analog input is tied to analog ground. windows is a registered trademark of the microsoft corporation.
EVAL-AD974CB C4C rev. 0 jumper designation function jp14 jp14 determines the source of the analog channel 1 input of the ad974. to supply the ad974 analog channel 1 input signal directly from the smb connector, j3, set jp14 to position b. set jp14 to position a to select the op amp output. jp15, jp16 these two jumpers are used to select the con figuration of the op amp, u3. to con figure the op amp as an inverter, install the header shunt of jp15 to position a and jp16 to position b. to configure the op amp as a noninverter, install the header shunt of jp15 to position b and jp16 to position a. jp17 jp17 selects the digital power source for the ad974-cb digital interface circuitry. install the jumper to provide a single +5 v supply to all of the on-board components. remove this header shunt to separate the analog supply for the ad974 from the supply for the digital interface circuitry. when used in conjun ction with the eval- control board, v ana and v dig are respectively the +5 v and vdd from the 96-pin connector. when this header shunt is installed, jp28 must also be installed. jp18 with jp19 in position b, the header shunt for jp18 allows the positive supply voltage of op amp, u3, to come from either connector p3 (position a), or the +12 v supply from the eval-control board (position b). jp19 with jp19 set to position a, the positive supply for the op amp, u3, is connected to vana. when jp19 is set to position b, u3s positive supply voltage is connected to either the +12 v from the eval-control board (jp18 position b), or the external supply (+v cc ) from connector p3 (jp18 position a). jp20 with jp21 in position a, the header shunt for jp20 allows the negative supply voltage of op amp, u3, to come from either connector p3 (position b), or the C12 v supply from the eval-control board (position a). jp21 with jp21 set to position b, the negative supply for the op amp, u3, is connected to analog ground (agnd). when jp21 is set to position a, u3s negative supply voltage comes from either the C12 v from the eval-con- trol board (jp20 position a) or the external supply (Cv cc ) from connector p3 (jp20 position b). jp22, jp23 these two jumpers set the analog input ranges for channel 3 according to tables i through table iii. jp24, jp25 these two jumpers set the analog input ranges for channel 4 according to tables i through table iii. jp26, jp27 these two jumpers set the analog input ranges for channel 2 according to tables i through table iii. jp28 install jp28 when using a single +5 v supply for the eval-control board. thus, install jp28 when jp17 is connected.
C5C rev. 0 EVAL-AD974CB 20 u8 1,10,19 74hc541 v dig c21 0.1 m f nc 9 74hc595 c19 0.1 m f v dig 16 8 13 12 10 11 14 r9 49.9k v 7 6 5 4 3 2 1 15 qh qg qf qe qd qc qb qa qh v cc gnd g rclk srclk srclr ser u5 cs (c-10) d15 (c-19) d14 (c-18) d13 (b-18) d12 (a-18) d11 (b-17) d10 (b-15) d9 (b-14) d8 (b-13) d7 (b-11) d6 (b-10) d5 (b-9) d4 (b-7) d3 (b-6) d2 (b-5) d1 (b-3) d0 (b-2) avdd (a,b,c-32) +5v avss (a,b,c-31) C5v +12v (c-30) +12v C12v (a-30) C12v v cc (a,b,c-8) v dd irq2 (c-17) fl1 (b-1) fl0 (a-17) rfs0 (c-6) dr0 (c-5) sclk0 (a,c-7) sclk1 (a,c-3) f0 (a-1) dgnd (a,b,c-4,12,16,20) agnd (a,b,c-21,22,23,24, 25,26,29 b-27,28,30) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 busy 12 39 40 40-pin idc connector j4 u7 u7 u7 u7 23456789 busy 19 20 1 2 17 3 u8 busy a1 dclk data r/ c a0 16 4 u8 u8 12 8 u8 11 9 15 5 u8 14 6 u8 tp2 tp8 jp9 tp9 p4 20-pin idc connector jp8 jp6 jp7 p5 96-pin din connector v dig tp7 jp3 18 2 u9 j2 j5 r8 49.9 v r10 49.9k v 13 7 u8 a b jp2 v dig r7 49.9k v 18 2 a b jp1 u8 tp17 r6 49.9 v a b j1 jp4 b jp5 a tp3 tp11 28 27 26 25 24 23 22 21 20 19 18 17 16 15 u9 c7 0.1 m f v ana 10 11 12 13 14 9 8 7 6 5 4 3 2 1 agnd1 va3 vb3 va4 vb4 bip cap ref agnd2 r/ c v dig pwrd ext/ int dgnd vb2 va2 vb1 va1 v ana a0 a1 busy cs wr1 wr2 data dclk sync ad974 u1 17 3 tp6 tp10 c6 2.2 m f c4 2.2 m f c5 0.1 m f v ana c21 0.1 m f v ana gnd out +v 2.000mhz x1 c20 0.1 m f v ana v ana 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b qb qa cten d/ u qc qd gnd v cc a clk rco mx/mn load c d u6 74hc190 8 7 6 5 4 3 2 1 v ana c2 0.1 m f c3 1 m f ad780 nc +v in temp gnd o/p select nc v out trim c1 330 m f r5 1m v vr1 50k v b a jp10 r4 576k v v ana vr2 50k v jp23 jp22 b a b a jp27 jp26 b a b a jp25 jp24 b a b a ad845 u3 r2 499 v r1 1k v a b a b jp15 jp16 ain4 ain2 ain1 ain3 tp12 j3 j8 j6 j7 Cv cc c8 10 m f c9 0.1 m f jp11 b a b a jp12 a b jp13 tp1 b a jp14 +v cc c10 0.1 m f c11 10 m f r3 1k v c17 2nf 16 u7 1,8,12,14,15 74hc366 v dig c16 0.1 m f 20 u9 1,4C10,19 74hc541 v dig c22 0.1 m f jp20 b a b a jp21 Cv cc tp13 +v cc tp14 b a jp19 a b jp18 v ana p3 C12v +v cc agnd Cv cc +12v dgnd v dig p2 v dd tp4 c15 0.1 m f c14 10 m f v dig tp5 tp15 v ana jp17 jp28 c12 0.1 m f c13 10 m f +5v agnd v ana p1 tp16 ext dclk ext rclk r/ c u2 9 74hc595 c18 0.1 m f v dig 16 8 13 12 10 11 14 7 6 5 4 3 2 1 15 qh qg qf qe qd qc qb qa qh v cc gnd g rclk srclk srclr ser u4 figure 2. schematic
EVAL-AD974CB C6C rev. 0 figure 3. component side silkscreen (not to scale) figure 4. component side (not to scale) figure 5. ground layer (not to scale) figure 6. power layer (not to scale) figure 7. circuit side (not to scale)
C7C rev. 0 EVAL-AD974CB figure 8. setup screen figure 9. histogram screen
C8C e3407C1C10/98 printed in u.s.a. EVAL-AD974CB rev. 0 figure 10. fft screen
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